The present invention is generally directed to differential-to-single-ended (DSE) converters and, in particular, to a DSE converter that minimizes power consumption and provides an accurate 50% duty cycle.
In many conventional phase-locked loop (PLL) designs, the voltage-controlled oscillator (VCO) is implemented as a plurality of ring oscillator stages that produce fully differential output signals having output voltage ranges that are smaller than the range of the power supplies. However, if the fully differential outputs are used as digital clock signals, they generally must be converted to single-ended rail-to-rail outputs. These designs therefore require a differential-to-single-ended (DSE) converter to produce the required single-ended output clock signal.
Because a good duty cycle is often desired in a system clock, a DSE converter must produce an output that is as close to a 50% duty cycle as possible. One well-known conventional apparatus for performing DSE conversion uses a comparator with a differential input stage. However, an imperfect duty cycle is caused by the mismatch of the rise time and fall time of such a comparator. Various techniques have been employed to minimize such a mismatch, but because of the single-ended nature of the output, there will always be some systematic mismatch between rise time and the fall time. Another way to further improve the matching is to make the comparator fastxe2x80x94if both the rise time and the fall time are small, the mismatch between the two also is small. Unfortunately, this approach leads to high power consumption.
A DSE converter also may consume high power due to the operation of the phase-locked loop (PLL). During frequency acquisition, the voltage-controlled oscillator (VCO) may oscillate at frequencies above the final target. In cases where the initial loop filter voltage happens to be at a maximum (i.e., the positive power supply), the VCO can oscillate at frequencies far above the final lock target. In order for the PLL to lock successfully, the DSE converter must be able to operate properly not just at the target VCO frequency, but also at the maximum frequency the VCO can produce during acquisition. As a result the DSE converter is designed for high-frequency operation and consumes more power than necessary. In a low power PLL design, such as that used in a battery-powered device, the power consumption of the DSE converter may be a significant portion of the total power consumption.
Therefore, there is a need in the art for an improved differential-to-single-ended (DSE) converter that maintains a very accurate 50% duty cycle in a phase-locked loop (PLL) design. In particular, there is need for a DSE converter that operates at relatively low power and relatively high frequency while maintaining a very accurate 50% duty cycle.
The present invention provides a differential-to-single-ended (DSE) converter with good duty-cycle performance that uses two simple comparators and some logic circuits, wherein a differential ring oscillator generates the input signals. Low power consumption can be achieved by employing: 1) a circuit topology that is insensitive to mismatches of comparator rise and fall delays; and 2) a dynamic bias current.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide a differential-to-single-ended (DSE) converter that receives a positive differential input signal and a negative differential input signal and generates a single-ended output signal. The DSE converter comprises: 1) a first comparator having a non-inverting input coupled to the positive differential input signal and an inverting input coupled to the negative differential input signal; 2) a second comparator having an inverting input coupled to the positive differential input signal and a non-inverting input coupled to the negative differential input signal; 3) a first D flip-flop having an input connected to Logic 1 and clocked by a rising edge on an output of the first comparator; 4) a second D flip-flop having an input connected to Logic 1 and clocked by a rising edge on an output of the second comparator; and 5) a latch circuit having a first input coupled to an output of the first D flip-flop and a second input coupled to an output of the second D flip-flop, wherein a rising edge on an output of the first D flip-flop causes an output of the latch to change state and a rising edge on an output of the second D flip-flop causes the latch output to change state.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d, and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation. A controller may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with a controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.